The present invention relates to circuits for programming an output cell in a programmable logic device (PLD) circuit.
A typical PLD has an array of fuses or memory cells which can be programmed to configure the array to provide a number of desired logic functions. Often, this array will be used in conjunction with output cells which may include multiplexers, inverters or other circuitry for handling the outputs of the main fuse or memory array. One or more array outputs may be provided to each output cell. These output cells can have programmable elements in them, such as a multiplexer which can be programmed to select one or the other of its inputs. The programming data for the output cell is typically stored in separate fuses or memory cells. Because the output cells need to be programmed or configured properly prior to readout from the main array, these fuses or memory cells are physically located outside of the main array and next to the other logic elements of the output cell. This complicates the layout of a PLD chip and requires the duplication of sense amplifiers and addressing circuits which are used for the main array.